Probing single electrons across 300-mm spin qubit wafers
Nature volume 629, pages 80–85 (2024 )Cite this article
Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid-state electronic devices1,2,3, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern complementary metal–oxide–semiconductor (CMOS) industry. Equally important, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics such as qubit yield and voltage variation. Spin qubits1,4,5 based on electrons in Si have shown impressive control fidelities6,7,8,9 but have historically been challenged by yield and process variation10,11,12. Here we present a testing process using a cryogenic 300-mm wafer prober13 to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and investigate the transitions of single electrons across full wafers. We analyse the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300-mm scale. Together, these results demonstrate the advances that can be achieved through the application of CMOS-industry techniques to the fabrication and measurement of spin qubit devices.
Silicon quantum dot spin qubits1,4,5 have recently demonstrated single-qubit and two-qubit fidelities well above 99% (refs. 6,7,8,9), satisfying thresholds for error correction14. Today, integrated spin qubit arrays have reached sizes of six quantum dots9,15, with larger quantum dot platforms in 1D (refs. 16,17) and 2D (refs. 18,19) configurations also being demonstrated. To realize practical applications with spin qubit technology, physical qubit count will need to be increased substantially20,21. This will require fabricating spin qubit devices with a density, volume and uniformity comparable with those of classical computing chips, which today contain billions of transistors. The spin qubit technology has inherent advantages for scaling owing to the qubit size (approximately 100 nm), as well as—in the case of Si-based devices—a native compatibility with CMOS manufacturing infrastructure. It has therefore been posited that manufacturing spin qubit devices with the same infrastructure as classical computing chips can unlock the potential of spin qubits for scaling and provide a path to building fault-tolerant quantum computers with the technology.
