Lower Power Chips: What To Watch Out For
Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context of other issues.
With each new leading-edge process node, and with increasingly dense packaging, the potential for problematic interactions is growing. That, in turn, can lead to poor yield, costly re-spins, and field failures. As a result, architects and designers are examining possible interactions and various use cases much earlier in the design process. And they are looking for ways to manage increasingly complex designs, which can introduce a variety of bugs that may not show up in isolation.
“Many power management techniques, including multi-voltage power shutdown, can add significantly higher complexity to the design because it actually shuts down part of the operation of a design,” said Renu Mehra, R&D group director for the Digital Design Group at Synopsys. “As all the different parts of the design are talking to each other, it is easy to send a corruption from a dead part of the design to other parts of the design. This means we need to be very careful that we have properly isolated those pieces that will be shut down, so that the other pieces that are live are not getting corrupted. It’s very important to make sure that this is working well right from the very beginning. Also, it’s important to have a complete power intent right in the beginning before running simulation. Most simulation tools natively understand UPF and power intent, and are able to synthesize shut down parts of the design simultaneously with the live parts.”
Peter Greenhalgh, vice president of technology and fellow at Arm, agreed. “Certainly, low power design can introduce bugs,” he said. “Clock gating is one example where you want to be as aggressive as possible to save power, but risk being too aggressive in disabling the clock and creating a functional bug. Fortunately, there’s no verification difference between an overly aggressive clock gate enable and any other functional bug, which means standard verification techniques are sufficient to catch clock gate enable bugs.”
