The Increasingly Uneven Race To 3nm/2nm
An emphasis on customization, many more packaging options, and rising costs of scaling are changing dynamics across the industry.
Several chipmakers and fabless design houses are racing against each other to develop processes and chips at the next logic nodes in 3nm and 2nm, but putting these technologies into mass production is proving both expensive and difficult.
It’s also beginning to raise questions about just how quickly those new nodes will be needed and why. Migrating to the next nodes does boost performance and reduce power and area (PPA), but it’s no longer the only way to achieve those improvements. In fact, shrinking features may be less beneficial for PPA than minimizing the movement of data across a system. Many factors and options need to be considered as devices are designed for specific applications, such as different types of advanced packaging, tighter integration of hardware and software, and a mix of processing elements to handle different data types and functions.
“As more devices become connected and more applications become available, we’re seeing exponential growth in data. We’ve also seen fundamentally different workloads, and can expect to see more changes in workloads as data and different usage models continue to evolve. This data evolution is driving changes to hardware and a different need for compute than what was historically experienced,” said Gary Patton, vice president and general manager of design enablement at Intel, during a keynote at SEMI’s recent Advanced Semiconductor Manufacturing Conference. “We absolutely need to continue to scale the technology, but that’s not going to be enough. We need to address heterogeneous integration at the system level, co-optimization of the design in the process technology, optimization between software and hardware, and importantly, continue to drive AI and novel compute techniques.”
