Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify

Variation Making Trouble In Advanced Packages

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2022-06-23 16:00:12

Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when.

Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-tuned. This is why design rules are more restrictive as new nodes are introduced, then relax over time as those processes mature. But as new multi-chip/multi-chiplet architectures — including chips developed at more than one process node — replace or supplement feature shrinks as the best way to improve PPA, the number of sources and impacts of variation is growing.

Variation has many causes, and it comes in many forms. It can show up in everything from lithography to cleaning and polishing, or even in the gases used for etch or deposition. It also can manifest itself in different sources of noise that can affect signal integrity. And it can show up in the interconnects between chips in a package, or within the packaging itself.

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