PCIe 7.0 first official draft lands, doubling bandwidth yet again
Analysis The PCIe 7.0 spec is on track for release next year and, for many AI chip peddlers trying to push the limits of network fabrics and accelerator meshes, it can't come soon enough.
On Tuesday the PCI SIG consortium that steers the interface's development emitted version 0.5 of PCIe 7.0, and hailed it as the official first draft of the specification. The blueprint calls for 128GT/s per lane of raw throughput, continuing the generational doubling that we've come to expect from the peripheral component interconnect standard.
This higher performance will enable up to 512GB/s of bidirectional bandwidth from an x16 slot. That's compared to the 256GB/s that PCIe 6.0 devices will be capable of pushing when they start hitting the market later this year.
Other improvements coming with PCIe 7.0 include optimizations for power efficiency, latency, and reach. The third point is important because as bandwidth capacity increases, the distance signals can travel gets shorter. Retimers can be used to clean up and extend the signal, but they do add latency. This is why we tend to see at least one retimer per accelerator on modern GPU systems.
