Switch Lite Netlist Extraction at 6,000 Pixels Per Inch

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2024-02-11 14:30:03

This is the output data for a process I solo-developed for extracting the netlist from an assembled Printed Circuit Board, in this case, a Nintendo Switch Lite logic board. Electrical components are soldered to exposed mounting pads on the PCB, and layers of copper form connections between these pads creating electrical circuits. The full list of these interconnects is called the netlist, and when combined with the part and pad geometries, constitute a boardview. Couple that boardview with reference images of both sides of the PCB, and you have the output data.

There are 3 novel-ish innovations working together to make this happen. They are: A process to create geometrical and color-accurate panoramic images of assembled PCBs at 6,000 PPI. A point-and-click GUI to draw geometrical part/pad data over the panoramas, with support for adding/modifying other arbitrary data. My own PCB capable of powering an arbitrary number of pins one-by-one, reading the state of all pins between each step. Once I had that figured out, the process is to simply: Take all the images and stitch the bottom-side panorama, flip the board, desolder the RF Shields, then take all the images and stitch the top-side panorama. Use these 2 panoramas and other images against each other to further refine the geometrical and color accuracy. Import the completed panoramas into the GUI, and use it to lay down the initial part/pad geometries. Desolder every component individually and place them into unique binned locations for future analysis. Record the binned location and presumed reference designator in the GUI, correcting any discrepencies in the pad geometries made in Step 2. With all pads exposed and not-shorted, hook one lead of a DMM in continuity mode to the ground plane, and use the other lead to probe every single pad on the PCB. Record all hits into the GUI, merging them into a single net. Use the GUI to group remaining pads into net-fragments, based on visual connections in the two outer board layers. If there is no visible connection, assume it is it's own fragment. Use the GUI to record the order you solder wires from the extractor PCB pins to which net-fragments on the target PCB. Run the extractor. Power goes from the extractor PCB pin, down the wire, into the net-fragment, through all hidden connections in the PCB, into other net-fragments, up those wires, back into the extractor PCB, and are logged to create a complete mapping of all hidden connections. Use the GUI to merge all of the fragments into a completed netlist, based on the extractor mapping. Export all this data into a boardview file, pack it up with the panoramas, and then... Share and Enjoy. The final stats are 2,444 photographs stitched into the 2 panoramas, 760 parts desoldered into binned locations, and 1,917 wires used for a total of approximately 30,176 lead-free, bismuth-free, and halide-free solder joints used to extract the netlist. While this is only about 3 weeks of soldering work, process/software/hardware development took over a year and over $10,000.

You may have noticed the panoramas are actually at 2,000 PPI. That's because the 6,000 PPI versions are half a gigapixel, each. This causes problems. With everything. You can Torrent or Download them here.

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