Deschamps/Sutter/Canto Guide to FPGA Implementation of Algorithms

Introductory example 2.1 (square_root.vhd). A simple test bench ( square_root_tb.vhd). Algorithm 2.2, square root, version 2 (square_root_2.vhd). A simple test bench square_root_2_tb.vhd ).

Introductory example 2.3.1. A 7-to-3 Counter (seven_to_three.vhd). A simple test bench ( seven_to_three_tb.vhd). It uses a basic carry save adder (CSA) (

Final example of Elliptic curve scalar product. First using explicit datapath and control separation (scalar_product.vhd and scalar_product_data_path.vhd); and a second implementation not

Section 3.1.4 Interconection of pipelined component. Example 3.4 of scalar product in GF(2^m) using s elf timed pipeline (not a synthesizable circuit) (pipeline_ST.vhd). A simple test bench (test_pipeline_ST.vhd). Example 3.5 a self timed ripple carry adder (adder_ST2.vhd). A test bench for ripple carry adder (test_adder_ST2.vhd).

Section 3.2  Loop unrolling and digit-serial computation. A sequential restoring division algorithm (restoring.vhd). The partially unrolled version of the restoring divider with s=2 (unrolled_divider.vhd). A Digit Serial version of the restoring algorithm with D=2 (restoringDS.vhd).

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