Deep Dive on Altera Agilex™ 5 Architecture.
In our previous article, we introduced the Intel Agilex 5 FPGAs. In this article, we delve deeper into three key aspects of the Agilex 5 logic architecture: clocking, ALM (Adaptive Logic Modules), and DSP (Digital Signal Processing) elements. These form the nucleus of any solutions so it is critical we understand them in depth.
At the core of any FPGA design is the principle of synchronous operation, as such the ability to support multiple high-speed clocks within the FPGA becomes crucial. The era of using a single clock has passed; today, the average design incorporates 3 to 4 clocks (Wilson Research Group Survey 2022)This complexity necessitates the FPGA can manage several clocks efficiently across its architecture. As we will see Agilex FPGAs are optimized for high-performance, multi-clock environment.
Each Agilex device is segmented into various clock sectors, each supported by a three-level clock hierarchy. The first level delivers the clock to the sector via programmable routing from the clock source across one of 32 dedicated lines. The second level operates within the sector itself, providing 32 clocks that are routed horizontally and vertically around the sector. Clock multiplexors at each corner can be configured to manage clock distribution. Clocks enter the sector through vertical channels, facilitating the implementation of the third level of hierarchy, the row clock. Row clocks are distributed from the sector clock to each logic row and adjacent transceivers, with each row accessing six clock resources.
