Challenging myself to understand RISC-V
RISC-V is just an open source ISA (Instruction Set Architecture). An ISA is the software interface for the hardware. A single ISA can have many hardware implementations. In technical terms as ISA defines set of Instructions and how they behave such as:
Another important factor to understand is that RISC-V is a standard and not an implementation. This means that the entire ISA is defined in a huge latex file which can be found on Github.
The RISC-V is a well organized ISA and is divided into various categories and extensions in order to keep it as a modular design. The RISC-V is maintained the non profit organization called RISC-V foundation.
Implementing RISC-V System-on-Chip for Acceleration of Convolution Operation and Activation Function Based on FPGA (Field programmable gate arrays): FGPA are mostly for application specific integrated circuits. An example would be Intel using FGPA to prototype new chips. The objective of the paper was to design a RISC-V processor for specific tasks such as Convolution functions and activation functions. The result was that the RISC-V processor was faster than CPU + co-processor mode and used lesser than the CPU + GPU mode.
Towards deep learning using Tensorflow lite on RISC-V: This paper focuses on ISA extensions customized for machine learning kernels. The software infrastructure implemented was optimized for neural network execution. The following was integrated into Tensorflow lite. The result was that instructions was reduced by 8X.
