MRISC32 – Stabilizing the Base architecture

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2021-07-26 20:30:11

The MRISC32 instruction set architecture recently reached a seemingly insignificant but major milestone: As of version 0.2 of the ISA the key elements of the Base architecture have been fixed, and it is very unlikely that any changes will be made to it any time soon.

The Base architecture is the minimum subset of the MRISC32 ISA that a conforming implementation (e.g. a CPU) must support. The other modules further extend the capabilities of an MRISC32 implementation, but they are optional and are still under development.

In short the Base architecture includes the basic scalar integer instructions such as arithmetic, logic, memory load/store and branch operations. Among other things, it includes scalar instructions for:

I believe that this is a very good and competent subset of the ISA, while still being simple enough to implement even in lightweight CPU:s.

The things that I wanted to pin down were mostly related to instruction encoding and which instructions to include in the Base architecture.

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