Improving Verilog Four State Logic - by Chris Drake

Hardware-oriented data types are a powerful feature of Verilog RTL. Unlike in C, where the bits of builtin, integer data types can only take Boolean { 0, 1} values, Verilog allows you to assign the bits of a variable to 0, 1, X, and Z.

When the z value is present at the input of a gate or when it is encountered in an expression, the effect is usually the same as an x value. Notable exceptions are the metal-oxide semiconductor (MOS) primitives, which can pass the z value.

Starting with the first problem, there are at least two types of unknown values: 1) uninitialized or metastable, and 2) “don’t care”. It is important to make a distinction here, because these two categories should behave differently in simulation. The former are values that should always propagate pessimistically from inputs to outputs for debug and correctness checking. The latter are values that should always propagate optimistically from inputs to outputs, because the designer leaves them unspecified on purpose. Verilog’s problem is that unless you pay for extra “X Prop” licenses from an EDA vendor, both uses of x have identical simulation semantics. We’re only getting one x for the price of two (actually three if you count Synopsys VCS tmerge, vmerge, and xmerge modes)!

Moving to the second problem, high impedance values operate at a lower level of abstraction than register transfer level (RTL) design and verification code. The IEEE 1800-2017 description paragraph says “at the input of a gate … the effect is usually the same as an x value”. The listed exception is a MOS primitive. Gates, MOS primitives, and even the concept of impedance—the measure of opposition to current flow—are circuit design concerns. The RTL abstraction is concerned with the legal input/output values of registers. If we follow Uncle Dijkstra’s advice and separate concerns appropriately, the z encoding is not pulling its weight.

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