imec builds working forksheet transistors for 2nm, 1nm
Research lab imec in Belgium has shown working versions of a transistor structure that could be used for 2nm and 1nm chip designs
The forksheet devices have a short-channel control (SSSAT=66-68mV/dec) comparable to gate-all-around (GAA) nanosheet devices down to 22nm gate length. Dual work function metal gates are integrated at 17nm spacing between n- and pFETs, highlighting the key benefit of forksheet devices for advanced CMOS area scaling.
Unlike nanosheet devices, the forksheets are controlled by a tri-gate forked structure that has a dielectric wall in between the p- and nMOS devices before gate patterning. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p spacing than what is possible with either FinFET or nanosheet devices.
Simulations in 2019 showed this approach had better area and performance scaling to 2nm and 1nm than GAA devices as a result of the reduced Miller capacitance that comes from a smaller gate-drain overlap.
