For the past decade, TSMC has been operating at a fairly consistent cadence. The company started risk production of its latest node, 5-nanometer, in March 2019. 5-nanometer is expected to ramp around the second quarter of this – likely April or May timeframe as long as COVID-19 does not disrupt operations. This article sources its information from a number of places including Arm Techcon 2019, 65th IEEE IEDM conference, and ISSCC 2020. We are also a little disappointed that, despite the significance of the paper, TSMC’s IEDM paper lacked real substance and was accepted without meeting the conference high quality standard we have come to expect from IEDM.
TSMC has yet to disclose the exact device sizes for the N5 node, therefore we will stick to our own estimates. Our current estimates remain at 48 nm poly pitch and 30 nm metal pitch. Those dimensions yield an estimated device density of 171.3 MTr/mmÂ². At IEDM, TSMC reported 1.84x density improvement over the company’s own N7 node. Our estimates land at 1.87x which is reasonably close. The comparison isn’t perfect as they are comparing the density of a whole CPU block and we are not, but the numbers are reasonably close based on the available information. A ramp in April will mark exactly two years since TSMC ramped its 7-nanometer node. Impressively, it’s also just under 5 years since the company ramped its 16-nanometer node, their first FinFET device. From N16 to N5, TSMC is currently pushing out production nodes at Moore’s Law pace of 2x/2 years which is actually faster than the historical trend line.
In one of the figures in the IEDM paper, TSMC had an illustration of patterning fidelity of EUV. It’s hard to tell how much we can rely on the visuals that were attached to the IEDM paper but if we were to assume that the minimal metal pitch here is roughly 30 nm, the cell height is roughly ~6T (identical to N7) which works out to around a 180 nm cell height. The high-density cells are likely 2+2 yielding 8-fin high cells, but if the COAG meant a single-fin isolation, N5 might be 7-fin high. In other words, the fin pitch is likely 25-26 nm. TSMC did mention that there is an HPC cell variant which uses 3 fins. If we assume a 25 nm FP, the HPC cells are 225 nm tall or 7.5T (also identical to N7).