You can integrate an x-nm FPGA into a x-nm SoC and keep the flexibility and the performance of the original FPGA using eFPGA. But you can do better: in many designs the data paths can be hardwired for higher performance/lower cost while keeping the control path fully programmable using carefully written RTL. OR you can use this to integrate 7nm or 16nm FPGA into 22/28nm SoCs. See this article for examples.
FPGAs burn a lot of power: most of it for the high speed SERDES/PHYs and overdrive. When integrating an eFPGA into the SoC you eliminate the SERDES on both sides and dramatically reduce power and latency of the system. Also reducing cost by eliminating the huge silicon area of the SERDES/PHYs and other fixed IP that may not be used. Some say this can be as much as a 10x reduction in power and cost depending on the FPGA! There is a detailed article here.
When we port EFLX eFPGA to a process node we can optimize for maximum performance or for minimum power or somewhere in between depending on the application.