This repository is home to several cores which can be used to implement 100Base-X Ethernet PHYs, Hubs (Repeaters), and more. All cores are synchronous and are designed to be used in a single 125 MHz clock domain. These cores target Lattice iCE40 HX FPGAs (in terms of timing), but most modules are not specific to any FPGA.
This module implements an AXI-stream FIFO that can be “replayed” indefinitely. That is, it will store the first BUF_SIZE cycles in a BRAM, and when requested it will send them over the master interface again. Once the buffer is exhausted it will wait for a replay or continue command. After continuing, it acts as a regular synchronous FIFO. This module is intended to help implementing half-duplex Ethernet MACs.
This module implements the transmit half of a full- or half-duplex Ethernet MAC. It implements the full CS/CDMA algorithm, and automatically prepends an 8-byte preamble/SFD and appends a 4-byte FCS to the data. It currently only supports 100M ethernet, although 10M would be easy to add. I have no plans to support 1000M.
This module implements an AXI Stream to Wishbone bridge. This is not a more-typical DMA bridge, where streaming data is written in a fixed pattern. Rather, this module allows interactive or scripted examination and readout of a Wishbone bus. For more details on the protocol implemented by this bridge, refer to the UART-Wishbone Bridge documentation.