litex-hub/linux-on-litex-vexriscv
This project is an experiment to run Linux with VexRiscv-SMP CPU, a 32-bits Linux Capable RISC-V CPU written in Spinal HDL. LiteX is used to create the SoC around the VexRiscv-SMP CPU and provides the infrastructure and peripherals (LiteDRAM, LiteEth, LiteSDCard, etc...). All the components used to create the SoC are open-source and the flexibility of Spinal HDL/LiteX allow targeting easily very various FPGA devices/boards: Xilinx, Intel, Lattice, Microsemi, Efinix FPGAs are tested with very various configuration: SDRAM/DDR/DDR2/DDR3/DDR4 or HyperRAM RAMs, RMII/MII/RGMII/1000BASE-X Ethernet PHYs, SDCard (in SPI or SD mode), SATA, PCIe, etc...
On Lattice ECP5 FPGAs, the open source toolchain even allows creating full open-source SoC with open-source cores and toolchain!
This project demonstrates how high level HDLs framework like Spinal HDL, LiteX can enable new possibilities and complement each other. Results shown here are the results of a productive collaboration between various open-source communities.
/image%2F6283631%2F20210518%2Fob_919b9b_ubuntu-software-center-in-kali-linux.jpeg)
