neorv32/stnolting

I am currently working on an on-chip debugger (OCD) that is compatible to the RISC-V External Debug Support - Version 0.13.2. It will support the execution based debugging scheme.

I have tested the whole OCD complex in its early stage and the results are quite promising. I am using "Open On-Chip Debugger 0.11.0-rc1+dev (SiFive OpenOCD 0.10.0-2020.12.1)" (RISC-V port of OpenOCD; prebuilt binaries available from SiFive) on Windows 10 with a FTDI FT2232H-56Q Mini Module as JTAG adapter to test everything on real hardware. The NEORV32 + OCD runs on an Intel Cyclone IV board.

OpenOCD can successfully connect to the DM/CPU via the DTM. Executing abstract commands and configuring and running the DM's program buffer also works: OpenOCD is able to read the CPU's misa CSR 🚀

Running, halting and single-stepping the CPU also works already. Furthermore, OpenOCD can read arbitrary memory locations using the low-level mdw command:

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