TL;DR A small CPU design that can come in handy, a detailed code walkthrough, a good place to start learning about both Silice and RISC-V. The Ice-V i

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2021-06-21 01:00:07

TL;DR A small CPU design that can come in handy, a detailed code walkthrough, a good place to start learning about both Silice and RISC-V.

The Ice-V is a processor that implements the RISC-V RV32I specification. It is simple and compact (~100 lines when reduced, see image below), demonstrates many features of Silice and can be a good companion in projects. It is specialized to execute code from BRAM, where the code is baked into the BRAM upon synthesis (can be a boot loader later loading from other sources).

It is easily hackable and would be extendable to boot from SPI, execute code from a RAM, and connect to various peripherals. The example drives LEDs and an external SPI screen.

Note: Compling code for the processor requires a RISC-V toolchain. Under Windows, this is included in the binary package from my fpga-binutils repo. Under macOS and Linux there are precompiled packages, or you may prefer to compile from source. See see getting started for more detailed instructions.

Now that we have tested the Ice-V let's dive into the code! The entire processor fits in less than 300 lines of Silice code (~130 without comments).

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