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Trinity | Hackaday.io

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2021-07-19 02:30:07

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This project was created on 12/15/2014 and last updated 3 years ago.

The design will be fully ternary in the CPU core with binary SRAM for memory (using a binary coded trinary scheme). The goal is to operate the machine at around 1 million instructions per second.

Memory address will be 2-trites wide or else I'd be limited to only 729 trites of memory which is too little for my goals. This means a hybrid 6/12-trit architecture. Given the added complexity of double width registers it may make sense to build the whole machine at 12-trits wide. The main concern is the full adder which is very heavy on electronics.

All ALU operations store the result in A. All single parameter ALU operations use A as the source. All dual parameter operations use A and B as the source operands.

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