AMD presents revolutionary “chip stacking” technology to optimize die utilization

A new patent application from AMD suggests that the company is planning to integrate a “multi-chip stacking” method into its future processors. This could involve an overlapping arrangement of smaller chiplets and larger dies in a single package. The patent describes an innovative packaging strategy in which smaller chiplets are partially arranged under a larger die. The aim of this technique is to make the chip architecture more efficient. Stacking allows more functions to be accommodated in the same area, which makes better use of the available space. The technology could also enable an increase in the number of cores, larger caches and a higher memory bandwidth.

Another aspect of this arrangement is the reduction of interconnect latency. Closer placement of the components enables shorter communication paths between the elements. This could be particularly advantageous for data-intensive applications. In addition, the smaller, separate chiplets should allow more precise control of individual areas of the chip, which enables more efficient energy management.

AMD has already developed chip stacking technologies in the past. With the introduction of processors that have an additional “3D V-Cache” module, the company has taken its first steps in this area. The new patent shows that AMD wants to further develop these approaches to improve the efficiency and performance of its chips. According to the patent, the company intends to scale its chip designs so that additional chiplets can be added. This modularity could facilitate future adaptations and extensions to the architecture. At the same time, the new design offers potential to reduce manufacturing costs by using smaller dies that work in conjunction with a larger die.

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