A game-changer for IP designers: design-stage verification
By the time you read this article, you should be able to get Adiuvo Engineering’s new Leonidas Spartan 7 Tile . It went on sale for pre-order in August for £150.00. Unlike FPGA development boards, Adiuvo’s Leonidas Spartan 7 Tile is designed to be used as a component in a larger design. The 59x59mm tile is a circuit board with a periphery of castellated interconnect pads that will take 0.1-inch headers or will just solder down onto a larger PCB without the headers.
Adiuvo Engineering designed its Leonidas Spartan 7 Tile to be used as a component in your own design, making it easy to integrate an AMD/Xilinx Spartan 7 FPGA into your board. Image credit: Adiuvo Engineering
The Leonardo FPGA Tile incorporates a relatively small AMD/Xilinx Spartan 7 XC7S25 FPGA with 23,360 logic cells, 80 DSP blocks, and 45 BRAMs. The Tile also incorporates 256Mbits of QSPI EEPROM for configuration memory and 32Mbits of external SRAM. The Tile has 82 I/O connections, including power, ground, and JTAG pins along with 32 3v3 I/O pins and 41 I/O pins that have configurable I/O voltages. The reason for sourcing an FPGA in board (or Tile) form is to accelerate early prototype development by acquiring the FPGA in a format that permits hand wiring. The FPGA itself is packaged in a ball grid array (BGA).
One aspect of the Tile that’s not obvious from the specification: the board also handles all the supply voltages required by the FPGA. The board runs from a single 4.5V to 18V power supply and manages all the voltages required by the FPGA and the other on-board devices. This is a design detail that you need not bother with when using the Tile rather than developing your own chip-level, FPGA-based design.
