A cost-effective metallization scheme to address the resistance-capacitance (RC) delay at beyond 20nm metal pitches for multiple generations More than

Semi-damascene metallization: inflection point in back-end-of-line processing?

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2024-11-14 22:30:04

A cost-effective metallization scheme to address the resistance-capacitance (RC) delay at beyond 20nm metal pitches for multiple generations

More than five years ago, imec proposed semi-damascene as a new module approach to address the increasing RC delay concerns related to Cu dual-damascene in advanced technology nodes.

When used in combination with a patternable metal such as Ru, semi-damascene promises to be RC, area, cost and power efficient – offering an interconnect scaling path.

This article reviews the value proposition, summarizes challenges and potential solutions of state of the art Ru-based semi-damascene and calls upon the academic and industrial community to collaboratively clear the path towards industrial adoption.

In 1997, the introduction of Cu dual-damascene integration schemes in the back-end-of-line (BEOL) of logic and memory chips marked an inflection point in semiconductor history. Chip makers moved away from subtractive Al patterning to wet processes like Cu electroplating and chemical mechanical polishing (CMP). This radical transition was needed to cope with an increasing RC delay in Al-based interconnects, the result of an increasing resistance-capacitance (RC) product. Being cost-effective and applicable to multiple layers of the BEOL stack, Cu dual-damascene was set to enable many subsequent generations of logic and memory technologies.

But in a few years from now, the metal pitches within the most critical BEOL layers will drop below 20nm. When that happens, Cu dual-damascene, in turn, will run out of steam. As shrinking metal line dimensions approach Cu’s electron mean free path, the RC delay will increase dramatically. In addition, Cu metallization requires a barrier, a liner and a cap layer to ensure good reliability and prevent Cu from out-diffusing into the dielectric. But these extra layers start to consume a large share of the total available line width, meaning that the precious conductive area cannot be fully utilized by the interconnect metal itself. These issues force the chip industry to investigate alternative metallization schemes with better figures of merit at tight metal pitches.