TSMC to Start Risk Production Using 4nm Node in Q3
Taiwan Semiconductor Manufacturing Co. is on track to start risk production of chips using its N4 (4 nm) fabrication technology in the third quarter, according to TSMC and DigiTimes' sources in the semiconductor supply chain. The new node will enable chipmakers to slightly shrink the N5 design and further optimize power consumption and performance in 2022.
TSMC's N4 belongs to the company's N5 family that also includes N5, N5P, and N5HPC. While all of these technologies rely on both deep ultraviolet lithography (DUV) and extreme ultraviolet lithography (EUV), as well as have many things in common, they are still quite a bit different and are designed for differing applications.
TSMC's N5P is a performance-enhanced version of N5 that boosts frequency potential by up to 5% or decreases power consumption by up to 10% (at the same transistor count). The node offers a seamless migration from N5, so it should be fairly easy to migrate a design or IP from N5 to N5P should the designer need to increase performance (or decrease power consumption) of their system-on-chips (SoCs) now. This technology is believed to be available now.
N4 is a further evolution of N5 that will enable a 6% smaller die area via an optical shrink and some further power and performance advantages enabled by BEOL (back end of line) enhancements. It continues to use N5's design rules, design infrastructure, SPICE simulation programs, and IPs. Yet, N4 will use EUV scanners for more layers, which will reduce mask counts, process steps, and costs.
