Let’s start by speaking some truth. Nothing about the “5 nanometer” CMOS process has any real relationship to five actual nanometers and transis

No More Nanometers – EEJournal

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2024-11-05 19:00:06

Let’s start by speaking some truth. Nothing about the “5 nanometer” CMOS process has any real relationship to five actual nanometers and transistor size. That train jumped off the rails years ago, and the semiconductor industry has inflicted tremendous self-harm by perpetuating the nanometer myth. 

I hear you. “The world has a billion problems, and nanometer nodes ain’t one!” But, hear me out. In the early, heady days of Moore’s Law, it made sense to characterize processes by gate length (L g ). We had about a gazillion semiconductor fabs around the world, and they needed some standardized way to, well, do anything at all, actually. But as the decades have marched past, describing semiconductor processes with length metrics based hypothetically on gate size has long since veered into the land of fiction.

Intel held the line from “10 micron” in 1972 through “0.35 micron” in 1995, an impressive 23-year run where the node name matched gate length. Then, in 1997 with the “0.25 micron/250 nm” node they started over-achieving with an actual L g of 200 nm – 20% better than the name would imply. This “sandbagging” continued through the next 12 years, with one node (130nm) having  L g of only 70nm – almost a 2x buffer. Then, in 2011, Intel jumped over to the other side of the ledger, ushering in what we might call the “overstating decade” with the “22nm” node sporting an  L g of 26 nm. Since then, things have continued to slide further in that direction, with the current “10nm” node measuring in with an  L g of 18 nm – almost 2x on the other side of the “named” dimension.

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